Structure of horizontal surrounding gate flash memory cell

ABSTRACT

The present invention discloses a structure of a horizontal surrounding gate (HSG) flash memory cell and a method for manufacturing the same. The HSG flash memory cell of the present invention is located on a trench of an isolation region, and a channel region of the HSG flash memory cell composed of a semiconductor film is encompassed by a tunneling oxide layer, a floating gate, and a control gate in sequence. The floating gate and the control gate are also formed on the trench below the channel region. Therefore, the leakage current of the channel can be improved, and the short channel effect cannot be induced by junction depth of a source/drain. Furthermore, the coupling capacitor between the control gate and the floating gate is increased easily by increasing the depth of the trench.

FIELD OF THE INVENTION

[0001] The present invention relates to a process for manufacturing aflash memory, and more particularly, to a structure of a horizontalsurrounding gate (HSG) flash memory cell and a method for manufacturingthe same.

BACKGROUND OF THE INVENTION

[0002] As semiconductor process technologies continue improving,computers, telecommunication products, network products, and informationappliances (IA) are developed vigorously. To scale down the size ofsemiconductor devices is the primary motivation to drive thesemiconductor process technologies. By scaling down devices size, theperformance, such as the changing speed of devices and the powerconsumption of devices, can then be improved, and the functions thereof,such as data storage, logic operation, and information processing, canbe enhanced. Therefore, the cost can be reduced. Especially, forsemiconductor memory devices that have a very important share in themarket have strict demands about the diminution of device size.

[0003] According to the functional differences, memory devices can bedivided into a random access memory (RAM) and a read only memory (ROM).The ROM does not lose the stored data even with the interruption ofsupplying power and is thus called as a nonvolatile memory. Contrarily,the RAM must keep the supplying power uninterruptedly for reserving thestored data and is thus called as a volatile memory. In addition,according to the ways for storing data, the ROM can be further dividedinto a mask read only memory (MROM), an erasable programmable ROM(EPROM), an electrically erasable programmable ROM (EEPROM), and a flashmemory, etc. Also, according to the structural difference, the RAM canbe further divided into a dynamic RAM (DRAM) and a static RAM (SRAM).

[0004] As the increasing popularization of portable electric devices,imperious demands for light, handy, and dependable storage devices areinduced. Regardless of digital cameras, notebooks, personal digitalassistants (PDA), digital music players, or mobile phones, etc, they allneed a dependable and convenient method to store and transmit data.Because the data stored in a flash memory can be kept after the power isshut off, flash memory devices are widely applied in the portableelectric devices.

[0005] Referring to FIG. 1, FIG. 1 shows a cross-sectional view of aconventional stacked gate flash memory cell structure. A flash memorycell 100 is formed on a semiconductor substrate 102, and a tunnelingoxide layer 108, a floating gate 110, a dielectric layer 112, and acontrol gate 114 of the flash memory cell 100 are stacked and formed onthe semiconductor substrate 102 in sequence. A source 104 and a drain106 of the flash memory cell 100 are formed by a thermal diffusionmethod or an ion implantation method to dope ions into the substrate102. Typically, the floating gate 110 and the control gate 114 arecomposed of polysilicon, and thus the dielectric layer 112 is called asan inter-poly dielectric (IPD) layer. Besides, the dielectric layer 112is usually formed by stacking three material layers, i.e.oxide/nitride/oxide (ONO), thereby to provide a better blocking abilityfor preventing the chargers within the floating gate 110 from enteringthe control gate 114.

[0006] Typically, the programming of the flash memory cell 100 isperformed by a channel hot electron injection (CHEI) method. Forexample, the channel hot electron injection method is to set thesubstrate 102 and the source 104 to 0 V, and the drain 106 to about 3 V,and to connect the control gate 114 to a power of high voltage, such as12 V. At this time, the electrons of the source 104 are driven by thevoltage of the drain 106 to pass through the channel region 105 and movetoward the drain 106, and the energy of electrons is increased by theacceleration from the high channel electric field. Especially in thechannel region 105 that is adjacent to the drain 106, the energy ofelectrons is greatly increased, thereby inducing the hot electroneffect. As a result of the hot electron effect, the electrons haveenough energy to exceed the potential barrier of the tunneling oxidelayer 108. At the same time, the attraction resulted from the highvoltage of the control gate 114 drives the electrons to pass through thetunneling oxide layer 108 and inject into the floating gate 110.

[0007] In addition, the erasing action of the flash memory cell 100 isperformed by a Fowler-Nordheim (FN) tunneling effect. The FN tunnelingeffect erasing method can be divided into a channel erasing method and asource/drain erasing method. In the channel erasing method, the controlgate 114 is supplied with a negative voltage or is grounded, and thechannel region 105 is supplied with a high voltage, such as 12 V,thereby attracting the electrons of the floating gate 110 into thechannel region 105 to complete the data erasing. In the source/drainerasing method, the control gate 114 is supplied with a negative voltageor is grounded, and the source 104 and/or the drain 106 are suppliedwith a high voltage, such as 12 V, thereby attracting the electrons ofthe floating gate 110 into the source 104 and/or the drain 106 tocomplete the data erasing.

[0008] As semiconductor process technologies continue enhancing,although the supplied voltage needed for performing the programming anderasing of the flash memory cell 100 is reduced, yet the electric fieldfor programming and erasing the flash memory cell 100 still needs thesame intensity. Without changing the programming/erasing voltage of theflash memory cell 100, it is very difficult to achieve the desiredvoltage of programming/erasing while the supplied voltage is reduced. Atpresent, there are two methods can be used to reduce theprogramming/erasing voltage of the flash memory cell 100. The firstmethod is to decrease the thickness of the tunneling oxide layer 108,and the second method is to increase the capacitor coupling ratiobetween the control gate 114 and the floating gate 110. Since thethickness of the tunneling oxide layer 108 multiplies the electric fieldused to program/erase the flash memory cell 100 is proportional to thevoltage for programming/erasing the flash memory cell 100, decreasingthe thickness of the tunneling oxide layer 108 can reduce the voltagefor programming/erasing the flash memory cell 100. However, in order tokeep the reliability of the flash memory cell 100, the thickness of thetunneling oxide layer 108 is preferred to be more than 80 Å, and isabout 100 Å more preferably. Hence, there is not much room left fordecreasing the thickness of the tunneling oxide layer 108. In addition,increasing the capacitor coupling ratio between the control gate 114 andthe floating gate 110 can increase the floating gate 110 voltage coupledfrom the control gate 114, so that the voltage needed to be supplied toprogram/erase the flash memory cell 100 can be reduced. However, in thetypical flash memory cell 100 process, increasing the capacitor couplingratio between the control gate 114 and the floating gate 110 usuallyleads to an increase in the size of the flash memory cell 100 and theprocess cost.

[0009] Furthermore, since there is not much room left for decreasing thethickness of the tunneling oxide layer 108, when the supplied voltage isreduced, the electrons ejecting from the source 104 though the channelregion 105 to the drain 106 cannot be controlled effectively.Especially, as the device size continues reducing to make the gateregion decrease continuously, so that the leakage current of thesub-channel area far from the gate under the channel region 105 isgetting more serious. Particularly, for the flash memory cell 100 usingthe source/drain erasing method, the source 104/drain 106 need a largerjunction depth. Thus, the leakage current is getting worse.

SUMMARY OF THE INVENTION

[0010] According to the aforementioned conventional flash memory cellstructure, the leakage current between a source and a drain is gettingworse as devices scaled down. Further, the coupling capacitor between acontrol gate and a floating gate cannot be increased effectively withoutincreasing the cell size and the processing cost.

[0011] Therefore, one major object of the present invention is toprovide a structure of a HSG flash memory cell, wherein a channel regionof the HSG flash memory cell is a thin film surrounded and encompassedby a floating gate and a control gate in sequence, thereby effectivelyimproving the leakage current between a source and a drain. Besides, thechannel region is surrounded by the floating gate and the control gate,so that the current of the flash memory cell of the present inventioncan be conducted in the both sides of the channel region, and thecurrent of the flash memory cell at the onstate is larger than thecurrent of the conventional flash memory cell.

[0012] Another object of the present invention is to provide a structureof a HSG flash memory cell formed on a trench. A floating gate and acontrol gate of the HSG flash memory cell encompass a channel filmtraversed over the trench, and the HSG flash memory cell is also formedon a space between the channel film and the bottom of the trench. Byincreasing the depth of the trench, the overlap area between thefloating gate and the control gate can be increased, so that a capacitorcoupling ratio between the floating gate and the control gate can beincreased. Therefore, without increasing the size of the flash memorycell, the larger capacitor coupling ratio can increase the couplingvoltage of the floating gate, and reduce the programming/erasing voltageof the flash memory cell.

[0013] A further object of the present invention is to provide a methodfor manufacturing a HSG flash memory cell. After a trench with a sizelarger than a channel is formed on a channel region, and a plurality ofspacers are fabricated beside a sidewall of the trench, a sacrificiallayer is filled into the trench. Then, after a channel film is formed onthe sacrificial layer, the sacrificial layer inside the trench isremoved, so that the channel film traverses over the spacers as asingle-plank bridge, and a space is formed between the channel film andthe bottom of the trench. By controlling the depth of the space betweenthe channel film and the bottom of the trench, the overlap area betweena floating gate and a control gate formed in the space sequentially canbe adjusted to improve the capacitor coupling ratio between the floatinggate and the control gate.

[0014] According to the aforementioned major object, the presentinvention further provides a structure of a HSG flash memory cell,comprising: a substrate, wherein the substrate comprises an isolationregion, a channel region, and a trench located on the isolation regionformed thereon, and the size of the isolation region is larger than thesize of the channel region, and the entire channel region is covered bythe isolation region; a source and a drain located beside two sides ofthe channel region respectively; a plurality of spacers located beside asidewall of the trench and on the isolation region; a crystallizedsemiconductor film is located on a portion of the spacers, wherein thecrystallized semiconductor film is connected with the source and thedrain respectively; an oxide layer surrounding and encompassing thecrystallized semiconductor film; a floating gate, wherein the oxidelayer is surrounded and encompassed by a portion of the floating gate,and the spacers, the isolation region, and the trench are covered by another portion of the floating gate, and the material of the floatinggate is polysilicon; a dielectric layer, wherein the portion of thefloating gate is surrounded and encompassed by a portion of thedielectric layer, and the other portion of the floating gate is coveredby an other portion of the dielectric layer; and a control gate, whereinthe portion of the dielectric layer is surrounded and encompassed by thecontrol gate, and the other portion of the dielectric layer is coveredby the control gate, and the material of the control gate is polysiliconor polycide.

[0015] According to the further object mentioned above, the presentinvention further provides a method for manufacturing a HSG flash memorycell, the method comprising: providing a substrate, wherein thesubstrate comprises an isolation region and a channel region formedthereon, and the size of the isolation region is larger than the size ofthe channel region, and the entire channel region is covered by theisolation region, and the isolation region is filled with an insulatingmaterial; removing a portion of the insulating material in the isolationregion to form a trench on the isolation region in the substrate;forming a plurality of spacers in the trench and beside a sidewall ofthe trench; forming a sacrificial layer to cover the isolation region,the trench, and the spacers, wherein the trench is filled with thesacrificial layer, and the spacers and the sacrificial layer areselected from different dielectric materials; forming an amorphoussemiconductor film to cover the substrate, the spacers, and thesacrificial layer; performing a re-crystallization step to make theamorphous semiconductor film covered on the substrate integrate into thesubstrate, and to make the amorphous semiconductor film located on theisolation region change into a crystallized semiconductor film, whereinthe temperature of the re-crystallization step is between about 500° C.and about 600° C., and the duration of the re-crystallization step isbetween about 0.5 hour and about 6 hours; removing a portion of thecrystallized semiconductor film to leave an other portion of thecrystallized semiconductor film located on the channel region, and toexpose a portion of the spacers and a portion of the sacrificial layer;removing the sacrificial layer to expose a bottom of the trench, so asto form a hollow region constituted by an other portion of thecrystallized semiconductor film, the spacers, and the bottom of thetrench, and to form a plurality of slots between the other portion ofthe crystallized semiconductor film and the trench; forming an oxidelayer to cover the remaining portion of the crystallized semiconductorfilm, wherein the oxide layer is a tunneling oxide layer; forming afloating gate to cover the oxide layer, a sidewall of the hollow region,and a bottom of the hollow region; forming a dielectric layer to coverthe floating gate, wherein the dielectric layer is a stacked structurecomposed of oxide/nitride/oxide; and forming a control gate to cover thedielectric layer, wherein the material of the control gate ispolysilicon or polycide. Furthermore, a source and a drain of the HSGflash memory cell of the present invention can be formed before theformation of the amorphous semiconductor film, or after the formation ofthe control gate, by using, for example, an ion implantation method, todope ions into the substrate beside two sides of the channel region.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The foregoing aspects and many of the attendant advantages ofthis invention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

[0017]FIG. 1 is a cross-sectional view of a conventional stacked gateflash memory cell structure; and

[0018]FIG. 2 to FIG. 15 are flow schematic diagrams of manufacturing aHSG flash memory cell in accordance with a preferred embodiment of thepresent invention, wherein FIG. 3 is a top view of FIG. 2, FIG. 7 is atop view of FIG. 6, FIG. 8 is a top view of FIG. 9, FIG. 10 is a topview of FIG. 11 and FIG. 12, and FIG. 13 is a top view of FIG. 14 andFIG. 15.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0019] With the popularization of portable electron products, the demandof flash memory rises substantially. How to develop a new generationflash memory and scale down the size of flash memory cell has become avery important R & D trend. The present invention discloses a structureof a HSG flash memory cell and a method for manufacturing the same. Byapplying the HSG flash memory cell of the present invention, the leakagecurrent between a source and a drain can be improved effectively, andthe cell current at on-state can be increased. In addition, a highercapacitor coupling ratio between a floating gate and a control gate isobtained to achieve the purpose for reducing a programming/erasingvoltage of the flash memory cell. In order to make the illustration ofthe present invention more explicitly and completely, the followingdescription and the drawings from FIG. 2 to FIG. 15 are stated.

[0020] Referring to FIG. 2 and FIG. 3, FIG. 3 is a top view of FIG. 2.First, a plurality of isolation regions 202 (only show the isolationregion 202 located in a predetermined device region 212) are formed on asemiconductor substrate 200, wherein the predetermined device region 212mainly comprises of a source region 208, a channel region 204, and adrain region 210. At present, the isolation region 202 of asemiconductor device is usually fabricated by using a shallow trenchisolation (STI) process. A trench-like opening is first formed on thesubstrate 200, and the trench-like opening is then filled with aninsulating material to form the isolation region 202. In the presentinvention, the size of the isolation region 202 is larger than that ofthe channel region 204, as shown in FIG. 3. Then, a portion of theinsulating material is removed by using, for example, an etching method,so as to form a shallower trench 206 on the isolation region 202.

[0021] Referring to FIG. 4, after the trench 206 is formed, a dielectricfilm (only show the spacers 214) is first deposited to cover thesubstrate 200, the isolation region 202, and the trench 206. Thedielectric film is etched by using, for example, an anisotropic etchingmethod, to form spacers 214 beside the sidewall of the trench 206 on theisolation region 202. The material of the spacers 214 can be siliconoxide and silicon nitride, etc, and the spacers 214 can be used toisolate the gate and source 218/drain 220 (shown in FIG. 5) formedsequentially. At this time, a sacrificial layer 216 is formed to coverthe substrate 200, the spacers 214, and the isolation region 202, and tofill the trench 206, wherein the sacrificial layer 216 is made of adielectric material, such as silicon nitride and silicon oxide, etc.However, the material of the sacrificial layer 216 has to be differentfrom the material of the spacers 214 to avoid damaging the spacers 214during the removal of the sacrificial layer 216. The sacrificial layer216 is preferred to have a chemical mechanical polishing (CMP) ratesimilar to the substrate 200, and to have a high etching selectivitywith respect to both the substrate 200 and the isolation region 202.Then, the sacrificial layer 216 is planarized by, for example, achemical mechanical polishing method, to remove the sacrificial layer216 located on the substrate 200 and to reserve the sacrificial layer216 in the trench 206. Ions are doped into the source region 208 and thedrain region 210 on the substrate 200 by, for example, an implantationmethod, so that a source 218 and a drain 220 are formed beside thechannel region 204, as shown in FIG. 5. As the source 218 and the drain220 are N⁺ type, the flash memory cell is N type; as the source 218 andthe drain 220 are P⁺ type, the flash memory cell is P type. In addition,the source 218 and the drain 220 can be formed by an implantationmethod, etc, after the control gate structure of the flash memory cellis formed.

[0022] Referring to FIG. 6 and FIG. 7, FIG. 7 is a top view of thestructure shown in FIG. 6. An amorphous semiconductor film (not shown)is deposited to cover the substrate 200, the source 218, the drain 220,the sacrificial layer 216, and the spacers 214. A re-crystallizationstep is performed on the amorphous semiconductor film by, for example, asolid phase epitaxy technique, so as to make the amorphous semiconductorfilm change into a single crystal silicon semiconductor film. There-crystallization step of the amorphous semiconductor film is performedfor a duration between about 0.5 hour and about 6 hours under atemperature between about 500° C. and about 600° C. As the amorphoussemiconductor film on the substrate 200, the source 218, and the drain220 will grow along the original lattice direction and integrate withthe substrate 200, the source 218, and the drain 220. Hence, acrystallized semiconductor film 222 is formed on the sacrificial layer216 and the spacers 214 on the isolation region 202. The crystallizedsemiconductor film 222 is doped with N type impurity (for P type flashmemory cell) or P type impurity (for N type flash memory cell). However,the doping step can also be performed in-situ while the amorphoussemiconductor layer is deposited. The crystallized semiconductor film222 is connected with the source 218 and the drain 220 respectively tobe used as the channel of the flash memory cell of the presentinvention. Then, the crystallized semiconductor film 222 outside thedevice region 212 is removed to expose a portion of the spacers 214 anda portion of the sacrificial layer 216, as shown in FIG. 7.

[0023] Referring to FIG. 8 and FIG. 9 simultaneously, FIG. 9 is across-sectional diagram alone hatch I-I in FIG. 8. The remainder of thesacrificial layer 216 is removed to expose the bottom of the trench 206by performing an etching step along the exposed portion of thesacrificial layer 216. Accordingly, a hollow region 224 is formedbetween the crystallized semiconductor film 222, the spacers 214, andthe bottom of the trench 206, as shown in FIG. 9. Furthermore, aplurality of slots 226 are formed between the crystallized semiconductorfilm 222 and the trench 206, as shown in FIG. 8.

[0024] Then, referring to FIG. 10, FIG. 11, and FIG. 12, wherein FIG. 11is a cross-sectional diagram alone hatch II-II in FIG. 10, and FIG. 12is a cross-sectional diagram alone hatch III-III in FIG. 10. An oxidelayer 228 is first formed to surround and encompass the crystallizedsemiconductor film 222, and to cover the substrate 200. The oxide layer228 surrounding the crystallized semiconductor film 222 is used to as atunneling oxide layer of the flash memory cell of the present invention,and in order to keep the device reliability, the thickness of the oxidelayer 228 is preferred to be more than 80 Å, and is about 100 Å morepreferably. Subsequently, a material, such as polysilicon and amorphous,of a floating gate 230 is deposited to surround and encompass the oxidelayer 228, and to cover the bottom and the sidewall of the hollow region224. The material of the floating gate 230 and the oxide layer 228outside the trench 206 are removed by, for example, an anisotropicetching method, so that a structure shown in FIG. 11 and FIG. 12 isformed. As shown in FIG. 10 and FIG. 12, the slots 226 cannot be coveredup or filled up to make sure that the subsequent material layers can beformed successfully.

[0025] Referring to FIG. 13 to FIG. 15, FIG. 14 is a cross-sectionaldiagram alone hatch IV-IV in FIG. 13, and FIG. 15 is a cross-sectionaldiagram alone hatch V-V in FIG. 13. After the floating gate 230 isformed, a dielectric layer 232 is first formed to surround and encompassthe floating gate 230 (including the floating gate 230 located in thetrench 206) and the substrate 200. For example, the dielectric layer 232can be an inter-poly dielectric layer, and the dielectric layer 232 canbe an oxide/nitride/oxide (ONO) stacked material layer to provide apreferred blocking ability for preventing the chargers within thefloating gate 230 from entering a control gate 234 though the dielectriclayer 232. A material, such as amorphous, polysilicon, or polycide, ofthe control gate 234 is deposited to surround and encompass thedielectric layer 232 including the dielectric layer 232 in the trench206. Then, the control gate 234 is patterned to complete the structureof the HSG flash memory cell of the present invention, as shown in FIG.14 and FIG. 15.

[0026] The overlap area between the floating gate and the control gate234 of the present invention can be adjusted by varying the depth of thehollow region 224 between the crystallized semiconductor film 222 andthe bottom of the trench 206, and by this way, the capacitor couplingratio between the floating gate 230 and the control gate 234 can also beimproved.

[0027] The programming of the HSG flash memory cell of the presentinvention can use, for example, a channel hot electron injection (CHEI)method. The programming is performed by grounding the source 218 orsetting the source 218 voltage to 0 V, setting the drain 220 voltage toabout 3 V, connecting the control gate 234 with a high voltage, such asabout 12 V. The electrons of the source 218 are driven by thedifferential voltage between the source 218 and the drain 220 to passthrough the channel, i.e. the crystallized semiconductor film 222, andmove to the drain 220. The electrons are accelerated to have anincreasing energy by the high channel electric field while moving in thecrystallized semiconductor film 222. Especially, as the electrons areadjacent to the drain 220, the energy of the electrons is greatlyincreased, thereby inducing the hot electron effect. As a result of thehot electron effect, the electrons have enough energy to exceed thepotential barrier of the oxide layer 228. At the same time, theattraction resulted from the high voltage of the control gate 234 drivesthe electrons to pass through the oxide layer 228 and inject into thefloating gate 230 so as to complete the programming.

[0028] The erasing action of the HSG flash memory cell of the presentinvention can use, for example, a channel erasing method by means of theFN tunneling effect. The control gate 234 is grounded or supplied with anegative voltage, and the source 218 and/or drain 220 are supplied witha high voltage, such as about 12V. The electrons of the floating gate230 are attracted to pass through the crystallized semiconductor film222 into the source 218 and/or drain 220, so that the erasing of thedata is completed.

[0029] An advantage of the present invention is that the channel of theHSG flash memory cell structure in the present invention is acrystallized semiconductor film surrounded and encompassed by a floatinggate and a control gate. Therefore, not only the short channel effectcan be avoided, but also the leakage current between a source and adrain can be improved effectively, and current can be conducted in theboth sides of the channel, so that the flash memory cell current aton-state can be enhanced.

[0030] Another advantage of the present invention is that the overlaparea between a floating gate and a control gate is increased by justincreasing the depth of a trench without increasing the size of theflash memory cell. Therefore, the capacitor coupling ratio between thefloating and the control gate is increased, and the purpose of reducingthe programming/erasing voltage of the flash memory cell is obtained.

[0031] As is understood by a person skilled in the art, the foregoingpreferred embodiments of the present invention are illustrations of thepresent invention rather than limitations of the present invention. Itis intended to cover various modifications and similar arrangementsincluded within the spirit and scope of the appended claims, the scopeof which should be accorded the broadest interpretation so as toencompass all such modifications and similar structure.

What is claimed is:
 1. A structure of a horizontal surrounding gate(HSG) flash memory cell, comprising: a substrate comprising an isolationregion, a channel region, and a trench located on the isolation regionformed on the substrate, wherein the size of the isolation region islarger than the size of the channel region, and the channel region isall covered by the isolation region; a source and a drain, wherein thesource and the drain are located beside two sides of the channel regionrespectively; a plurality of spacers, wherein the spacers are locatedbeside a sidewall of the trench and on the isolation region; acrystallized semiconductor film located on a portion of the spacers,wherein the crystallized semiconductor film is connected with the sourceand the drain respectively; an oxide layer surrounding and encompassingthe crystallized semiconductor film; a floating gate, wherein the oxidelayer is surrounded and encompassed by a portion of the floating gate,and the spacers, the isolation region, and the trench are covered by another portion of the floating gate; a dielectric layer, wherein theportion of the floating gate is surrounded and encompassed by a portionof the dielectric layer, and the other portion of the floating gate iscovered by an other portion of the dielectric layer; and a control gate,wherein the portion of the dielectric layer is surrounded andencompassed by the control gate, and the other portion of the dielectriclayer is covered by the control gate.
 2. The structure of the HSG flashmemory cell according to claim 1, wherein the material of spacers is adielectric material.
 3. The structure of the HSG flash memory cellaccording to claim 1, wherein the material of the spacers is siliconoxide.
 4. The structure of the HSG flash memory cell according to claim1, wherein the material of the spacers is silicon nitride.
 5. Thestructure of the HSG flash memory cell according to claim 1, wherein thecrystallized semiconductor film is formed by performing are-crystallization step on an amorphous semiconductor material.
 6. Thestructure of the HSG flash memory cell according to claim 1, wherein thecrystallized semiconductor film is a channel of the HSG flash memorycell.
 7. The structure of the HSG flash memory cell according to claim1, wherein the oxide layer is a tunneling oxide layer.
 8. The structureof the HSG flash memory cell according to claim 1, wherein the materialof the floating gate and the material of the control gate arepolysilicon.
 9. The structure of the HSG flash memory cell according toclaim 1, wherein the dielectric layer is an inter-poly dielectric (IPD)layer, and the dielectric layer is an oxide/nitride/oxide (ONO) stackedstructure.
 10. A structure of a horizontal surrounding gate (HSG) flashmemory cell, comprising: a substrate, wherein the substrate comprises:an isolation region; a channel region, wherein the size of the isolationregion is larger than the size of the channel region, and the channelregion is all covered by the isolation region; a trench located on theisolation region; and a source and a drain, wherein the source and thedrain are located beside two sides of the channel region respectively; aplurality of spacers located beside a sidewall of the trench; acrystallized semiconductor film located on a portion of the trench,wherein the crystallized semiconductor film is connected with the sourceand the drain respectively; an oxide layer; a floating gate; adielectric layer; and a control gate, wherein the crystallizedsemiconductor film is surrounded and encompassed by the oxide layer, aportion of the floating gate, a portion of the dielectric layer, and thecontrol gate in turn, and the trench and the spacers are covered by another portion of the floating gate, an other portion of the dielectriclayer, and the control gate in sequence.
 11. The structure of the HSGflash memory cell according to claim 10, wherein the material of thespacers is a dielectric material.
 12. The structure of the HSG flashmemory cell according to claim 10, wherein the crystallizedsemiconductor film is a channel of the HSG flash memory cell.
 13. Thestructure of the HSG flash memory cell according to claim 10, whereinthe oxide layer is a tunneling oxide layer.
 14. The structure of the HSGflash memory cell according to claim 10, wherein the material of thefloating gate is polysilicon and the material of the control gate ispolysilicon or polycide.
 15. A method for manufacturing a horizontalsurrounding gate (HSG) flash memory cell, comprising: providing asubstrate comprising a isolation region and a channel region formedthereon, wherein the size of the isolation region is larger than thesize of the channel region, and the channel region is all covered by theisolation region, and the isolation region is filled with an insulatingmaterial; removing a portion of the insulating material in the isolationregion to form a trench on the isolation region in the substrate;forming a plurality of spacers in the trench and beside a sidewall ofthe trench; forming a sacrificial layer to cover the isolation region,the trench, and the spacers, and the trench is filled up with thesacrificial layer; forming an amorphous semiconductor film to cover thesubstrate, the spacers, and the sacrificial layer; performing are-crystallization step to make the amorphous semiconductor filmcovering the substrate integrate into the substrate, and to make theamorphous semiconductor film located on the isolation region change intoa crystallized semiconductor film; removing a portion of thecrystallized semiconductor film to leave an other portion of thecrystallized semiconductor film located on the channel region, and toexpose a portion of the spacers and a portion of the sacrificial layer;removing the sacrificial layer to expose a bottom of the trench, so asto form a hollow region constituted by the other portion of thecrystallized semiconductor film, the spacers, and the bottom of thetrench, and to form a plurality of slots between the other portion ofthe crystallized semiconductor film and the trench; forming an oxidelayer to cover the other portion of the crystallized semiconductor film;forming a floating gate to cover the oxide layer, a sidewall of thehollow region, and a bottom of the hollow region; forming a dielectriclayer to cover the floating gate; and forming a control gate to coverthe dielectric layer.
 16. The method for manufacturing the HSG flashmemory cell according to claim 15, wherein before the step of formingthe amorphous semiconductor film is performed, the method furthercomprises forming a source and a drain in the substrate, and the sourceand the drain are located respectively beside two sides of the channelregion.
 17. The method for manufacturing the HSG flash memory cellaccording to claim 15, wherein after the step of forming the controlgate is performed, the method further comprises forming a source and adrain in the substrate, and the source and the drain are locatedrespectively beside two sides of the channel region.
 18. The method formanufacturing the HSG flash memory cell according to claim 15, whereinthe spacers is a dielectric material, and the sacrificial layer is another dielectric material.
 19. The method for manufacturing the HSGflash memory cell according to claim 15, wherein the sacrificial layerhas a high etching selectivity to the substrate and the insulatingmaterial in the isolation region, and a chemical mechanical polishing(CMP) rate of the sacrificial layer is approximately equal to a chemicalmechanical polishing rate of the substrate.
 20. The method formanufacturing the HSG flash memory cell according to claim 15, whereinthe temperature of performing the re-crystallization step is betweenabout 500° C. and about 600° C., and the duration of there-crystallization step is between about 0.5 hour and about 6 hours. 21.The method for manufacturing the HSG flash memory cell according toclaim 15, wherein the other portion of the crystallized semiconductorfilm is a channel of the HSG flash memory cell.
 22. The method formanufacturing the HSG flash memory cell according to claim 15, whereinthe oxide layer is a tunneling oxide layer.
 23. The method formanufacturing the HSG flash memory cell according to claim 15, whereinthe material of the floating gate is polysilicon and the material of thecontrol gate is polysilicon or polycide.
 24. The method formanufacturing the HSG flash memory cell according to claim 15, whereinthe dielectric layer is an inter-poly dielectric (IPD) layer, and thedielectric layer is an oxide/nitride/oxide (ONO) stacked structure.